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TMC2005
PRELIMINARY
5 Port HUB Controller Device
FEATURES
HUB Circuit for ARCNET Protocol (Data Rate From 156.25Kbps to 10Mbps) Able to Connect Various Transceivers Directly Device Includes TX/RX Timing Circuit for 5 Port Hub and Direction Control Circuit, Jitter Correct Circuit and Noise Cancel Circuit Easy to Design 8 or 12 Port Hub Can Connect with HYC9068 or HYC9088 in Normal Mode Can Connect with RS485 Transceiver, HYC2485S, HYC2488S, Opt Module and TTL Interface in Backplane Mode Supports both Normal and Backplane Mode at the Same Time for Media Conversion + 5V Single Power

GENERAL DESCRIPTION
When configuring a network, the maximum number of nodes and the maximum cable length are limited by the electric capacity of the transceiver. In this case, the network is expanded by an equipment called a "HUB" or "repeater". It maybe necessary to have a converter between coax, T/P and the fiber cable. It is easy to design a HUB or a repeater because the TMC2005 has various features for expanding such network. It can connect with HYC9088 and HYC9068, RS485 transceiver, HYC2485S, HYC2488S and TTL interface for optical module. It can connect with three different transceivers at the same time and convert the media of each. (The data rate cannot be converted. It is necessary to operate all nodes in the same network at the same data rate). The Hubs can be expanded by connecting two or more TMC2005 chips. By setting one of 5 ports to opendrain output. The Hub can be expanded to either 12 or 16 ports.
SMSC DS - TMC2005
Rev. 10/24/2000
(c) STANDARD MICROSYSTEMS CORPORATION (SMSC) 2000
80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123
Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC is a trademark of Standard Microsystems Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC DS - TMC2005
Page 2
Rev. 10/24/2000
TABLE OF CONTENTS
FEATURES......................................................................................................................................................................................... 1 GENERAL DESCRIPTION ................................................................................................................................................................ 1 PIN CONFIGURATION ...................................................................................................................................................................... 4 BLOCK DIAGRAM............................................................................................................................................................................. 5 DESCRIPTION OF PIN FUNCTIONS ............................................................................................................................................... 6 TX/RX Interface............................................................................................................................................................................ 8 Operating Mode Setup............................................................................................................................................................... 9 PLL ................................................................................................................................................................................................ 9 Other Signals ............................................................................................................................................................................10 OPERATIONAL DESCRIPTION.....................................................................................................................................................11 Direction Determination ..........................................................................................................................................................11 Direction Release ....................................................................................................................................................................11 Jitter Filter...................................................................................................................................................................................11 Option Feature for Jitter Filtering ...........................................................................................................................................12 APPLICATION NOTES ...................................................................................................................................................................13 PORT GROUP .................................................................................................................................................................................21 Various Setup............................................................................................................................................................................21 Example For Operation Mode Setup To Each Port ............................................................................................................21 Note for Unused port ...............................................................................................................................................................21 Example for Power-On Reset Circuit....................................................................................................................................21 CONNECTING THE TMC2005 WITH INTERNAL PLL................................................................................................................22 Method To Connect A Crystal Clock......................................................................................................................................23 CASCADING CONNECTION ..........................................................................................................................................................23 Ring Network With the TMC2005 ..........................................................................................................................................27 OPERATIONAL DESCRIPTION.....................................................................................................................................................29 MAXIMUM GUARANTEED RATINGS* ...................................................................................................................................29 STANDARD OPERATING CONDITION ................................................................................................................................29 DC CHARACTERISTIC - INPUT PIN.....................................................................................................................................29 DC CHARACTERISTIC - OUTPUT PIN ................................................................................................................................30 AC CHARACTERISTIC - CLOCK and RESET.....................................................................................................................30 TMC2005 60 PIN QFP PACKAGE OUTLINE...............................................................................................................................31
SMSC DS - TMC2005
Page 3
Rev. 10/24/2000
PIN CONFIGURATION
Package: 60-pin QFP Order Number: TMC2005
SMSC DS - TMC2005
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
RXFLT nPLLTST VDD2 XTLI XTLO VSS4 VDD4 VDD3 AVDD RO LP AGS AVSS VSS3 VSS5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MB RXINB1 LB TXENB0 SB RXINB0 VSS8 VDD6 TXENA1 MA RXINA1 LA TXENA0 SA RXINA0
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46
TXENB1 NC1 SE NC2 LE EXTRX ME VSS1 EXTTX VDD1 CKO VSS2 CKM2 CKM1 CKM0
TMC2005
VSS7 nPULSE1 nPULSE2 nP1BAK VDD5 nCKOEN nRST VSS6 nBJA nBJB nBJE nMBA nMBB nMBE nEXTOD
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
Page 4
Rev. 10/24/2000
BLOCK DIAGRAM
nBJB SE SB SA nBJE nMBE nMBA ME MB MA LE LB LA nEXTOD
nBJA
nMBB
RXINA0 RXINA1
NOT Circuit
OR Circuit
NOT Circuit
TXENA0 TXENA1
RXINB0 RXINB1
NOT Circuit
Direction Control Circuit
OR Circuit
NOT Circuit
TXENB0 TXENB1
EXTRX
NOT Circuit
OR Circuit
NOT Circuit
RXFLT
Output Control Circuit
EXTTX
Rx Buffer
Tx Pulse Gen.
nP1BAK nPULSE1 nPULSE2
DPLL
VSS1-8 VDD1-6
Clock Multiplier PLL XTLO XTLI AVDD AVSS nRST CKM0 CKM2 nPLLTST AVSS LP RO nCKOEN AND Circuit CKO
CKM1
SMSC DS - TMC2005
Page 5
Rev. 10/24/2000
DESCRIPTION OF PIN FUNCTIONS
QFP PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 NAME TXENB1 NC1 SE NC2 LE EXTRX ME VSS1 EXTTX VDD1 CKO VSS2 CKM2 CKM1 CKM0 RXFLT nPLLTST VDD2 XTLI XTLO VSS4 VDD4 VDD3 AVDD RO LP AGS AVSS VSS3 VSS5 nEXTOD nMBE nMBB nMBA nBJE nBJB nBJA VSS6 nRST nCKOEN VDD5 nP1BAK nPULSE2 nPULSE1 VSS7 RXINA0 INPUT/ OUTPUT OUTPUT INPUT DESCRIPTION Port B-1 TX output to media transceiver Reserved. It should be open Port EXT. Polar assignment for EXTRX input (0:active HI 1:active LO) Reserved. It should be open Port EXT. Polar assignment for EXTRX input (0:active LO 1:active HI) Port EXT. RX-Data input from media transceiver Port EXT. Output mode assignment of EXTTX (0:pulse output 1:TX enable output) Ground Port EXT. Output to media transceiver Power Supply Clock Output Ground Network Speed (data rate) setting Network Speed (data rate) setting Network Speed (data rate) setting Test Pin. It should be open Test Pin for PLL. Must always connect to VDD Power Supply X'tal input/External clock input X'tal output Ground Power Supply Power Supply Analog Power Supply VCO output for internal PLL Connection pin to loop filter for internal PLL Analog sense pin for internal PLL Analog Ground Ground Ground Port EXT. Open-drain mode (0:open-drain output 1:normal output) Port EXT. Noise cut (0:on 1:off) Port EXT. A0/A1 Noise cut (0:on 1:off) Port B0/B1 Noise cut (0:on 1:off) Port EXT. Jitter correct mode (0: big jitter mode 1:normal mode) Port A0/A1 Jitter correct mode (0: big jitter mode 1:normal mode) Port B0/B1 Jitter correct mode (0:big jitter mode 1:normal mode) Ground Internal reset signal (active low) Enable of CKO output Power Supply nPULSE1 output (for backplane mode) nPULSE2 output (for normal mode) nPULSE1 output (for normal mode) Ground Port A-0 RX-data input from media transceiver
Pull-up
INPUT INPUT INPUT
Pull-up Pull-up Pull-up
OUTPUT OUTPUT INPUT INPUT INPUT INPUT INPUT INPUT OUTPUT
Pull-up Pull-up Pull-up Pull-up
OUTPUT OUTPUT INPUT
INPUT INPUT INPUT INPUT INPUT INPUT INPUT
Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up
INPUT INPUT OUTPUT OUTPUT OUTPUT INPUT
Pull-up Pull-up
Pull-up
SMSC DS - TMC2005
Page 6
Rev. 10/24/2000
QFP PIN NO. 47 48 49 50 51 52 53 54 55 56 57 58 59 60
NAME SA TXENA0 LA RXINA1 MA TXENA1 VDD6 VSS8 RXINB0 SB TXENB0 LB RXINB1 MB
INPUT/ OUTPUT INPUT OUTPUT INPUT INPUT INPUT OUTPUT
INPUT INPUT OUTPUT INPUT INPUT INPUT
DESCRIPTION Port A. Polar assignment for RXINA0/A1 output (0:active HI 1:active LO) Port A-0 TX output to media transceiver Port A. Polar assignment for TXENA0/A1 output (0:active LO 1:active HI) Port A-1 RX-data input from media transceiver Port A. Mode assignment for TXENA0/A1 (0:pulse output 1:TX enable output) Port A-1 TX output to media transceiver Power Supply Ground Port B-0 RX-data input from media transceiver Port B. Polar assignment for RXINA0/A1 input (0:active HI 1:active LO) Port B-0 TX output to media transceiver Port B. Polar assignment for TXENA0/A1 output (0:active LO 1:active HI) Port B-1 RX-data input from media transceiver Port B. Mode assignment for TXENA0/A1 (0:pulse output 1:TX enable output)
Pull-up
Pull-up Pull-up Pull-up
Pull-up Pull-up
Pull-up Pull-up Pull-up
Note:
Pull-up: Input with a pull-up resistor 70KO 30%
SMSC DS - TMC2005
Page 7
Rev. 10/24/2000
TX/RX Interface FEATURE RX Port NAME RXINA [0:1] RXINB [0:1] EXTRX SA, SB, SE INPUT/OUTPUT INPUT DESCRIPTION Setup the polarity by SA, SB, SE.
RX Port
Polar Assignment
INPUT
TX Port
TX Control
TXENA [0:1] TXENB [0:1] EXTTX nPULSE [1:2]
OUTPUT
TX Port
TX Data Output
OUTPUT
TX Port
nP1BAK
OUTPUT
TX Port
Polarity Setup
LA, LB, LE
INPUT
TX Port
Mode Setup
MA, MB, ME
INPUT
Setup the polarity of RXINA [0:1], RXINB [0:1], EXTTX. 0 : active H 1: active L TX data pulse (Mx=0) or TX enable signal (Mx=1). Setup TX mode by MA, MB, ME. Setup the polarity by LA, LB, LE TX pulse data into HYC9068SSK/9088S-SK when ARCNET chip is at normal mode. The pulse is always active Low. TX pulse data into RS485 driver or HYC2485S/2488S when ARCNET chip is at backplane mode. The pulse is always active Low. Setup the polarity of TXENA [0:1], TXENB [0:1], EXTTX. 0 : active L 1: active H Setup the mode of TXENA [0:1], TXENB [0:1], EXTTX. 0: Output TX pulse. (It is equivalent to nTXEN "OR" nP1BAK) 1: Output TX enable
SMSC DS - TMC2005
Page 8
Rev. 10/24/2000
Operating Mode Setup FEATURE Data rate setup NAME CKM [0:2] INPUT/ OUTPUT INPUT DESCRIPTION
Terminal to setup the data rate of TMC2005. CKM2 CKM1 CKM0 DIVISOR 0 0 0 16 0 0 1 8 0 1 0 4 0 1 1 2 1 0 0 1 1 0 1 1 1 1 0 Reserved 1 1 1 1 External clock is 20MHz. Refer to "VARIOUS SETUP" MULTIPLIER SPEED x1 156.25 Kbps x1 312.5 Kbps x1 625 Kbps x1 1.25 Mbps x1 2.5 Mbps x2 5 Mbps Reserved Reserved x4 10 Mbps
Noise cut mode
nMBA nMBB nMBE nBJA nBJB nBJE
INPUT
0: Cut off noise from received data 1: Don't cut off noise Setup "0" normally. Setup a jitter filter feature. Select a pulse as reference phase used by DPLL. 0: 2 nd pulse (big jitter mode) 1: 1 st pulse (normal mode) Setup a the use of EXTTX port. 0: Set EXTTX as open drain output and use as Ext. 1: Set EXTTX as normal output and use as 5 th port.
Big jitter mode
INPUT
Open drain mode
nEXTOD
INPUT
PLL FEATURE NAME LP INPUT/ OUTPUT OUTPUT DESCRIPTION
Using PLL: Connect to an external condenser "C1" for loop filter.
Using no PLL: must be open. VCO output Using PLL: Connect to an external resistor "R0" for loop filter. Using no PLL: must be open. Analog sense input. Using PLL: Connect to loop filter. Using no PLL: Connect to ground. Test pin for PLL. Must always connect to VDD. Analog power supply Using PLL: Analog power supply. There are some limits on PCB pattern. Using no PLL: Power supply (+5V) same as VDD1~6. Analog ground Using PLL: Analog ground. There are some limits on PCB pattern. Using no PLL: Use a ground same as VSS1~8.
RO
OUTPUT
AGS
INPUT
nPLLTST AVDD
INPUT
AVSS
SMSC DS - TMC2005
Page 9
Rev. 10/24/2000
Other Signals INPUT/ OUTPUT INPUT
FEATURES CRYSTAL INTERFACE
NAME XTLI
DESCRIPTION Connect a 20MHz crystal. When supplying an external clock, input the clock to this pin. Connect a 20MHz crystal. When supplying an external clock, it must be open. Reset for initializing TMC2005. (active Low) Output internal clock of TMC2005. Output control of CKO. 0: Output internal clock on CKO. 1: Always output Low level on CKO. Set "1" Normally. It must be open It must be open Power supply (+5V) Ground
CRYSTAL INTERFACE
XTLO
OUTPUT
SYSTEM RESET INTERFACE TEST PIN TEST PIN
nRST CKO nCKOEN
INPUT OUTPUT INPUT
TEST PIN TEST PIN POWER SUPPLY GROUND
RXFLT NC [1:2] VDD [1:6] VSS [1:8]
INPUT
SMSC DS - TMC2005
Page 10
Rev. 10/24/2000
OPERATIONAL DESCRIPTION Direction Determination All TX ports are set to disable mode in the initial state. When a signal is received from any RX ports, the circuit holds the port on receiving mode (disable TX) and changes the other ports to sending mode (disable RX). One port stays in RX and the rest change into TX after all. The circuit initializes the internal DPLL on the timing of received RX pulse, and the RX buffer circuit stores the RX data and filters its jitter. TX controlling circuit regenerates the stored RX pulse on nPULSE1, nPULSE2 and nP1BAK. The nPULSE1 and nPULSE2 are pulse output pins for transceivers (HYC9068S-SK/9088S-SK) of ARCNET normal mode. The nP1BAK is a pulse output pin for transceiver (HYC2485S/2488S and RS485 driver) of ARCNET back plane mode. When using optical transceiver, instead of these signals, TXENA [0:1], TXENB [0:1], EXTTX (MA, MB, ME = 0) must be used as TX data inputs of the optical transceiver. Direction Release On ARCNET protocol, each TX message starts with 6-bits of "1" ALERT and each data byte is lead by three bits (1, 1, 0) preamble. To control the HUBs direction, the circuit monitors this bit pattern and holds the state. If the end of the bit pattern comes, all TX ports return receiving mode (disable TX) again. The interval timer detects the end of the bit pattern. During data is on line, silent period is less than 4 uS* because at least one bit "1" among 10-bits is received while receiving the data. The minimum silent interval from the end of received data to the alert of the next data (the minimum time of changing the direction) is the chip turn around time (12.6 uS*) of ARCNET controller. The interval timer to detect the data end is set to 5.6uS by adding some margin to the above interval for neglecting the reflection on a cable. [Note] Numbers marked * are at 2.5Mbps operation. Jitter Filter To build a network with transceivers that introduce big jitter like ones for optical fiber, the old HUB that has direction control only may cause a transmission error because jitters on each HUB are added when several HUBs were connected in serial. The TMC2005 fixes that problem with jitter filtering and wave shaping through the following three steps. 1) Input Sampling The TMC2005 samples a data on a network by eight times clock of the network data. 2) Jitter Filtering (DPLL) The TMC2005 filters the jitter ( 100nS at 2.5Mbps) of network data sampled by 8X clock through the internal digital PLL and stores the data into the buffer. 3) Wave Shaping Output The TMC2005 re-synchronizes and regenerates the network data at the same clock as the data rate. The capability of the jitter filtering is shown below. DATA RATE 10Mbps 5Mbps 2.5Mbps 1.25Mbps 625Kbps 312.5Kbps 156.25Kbps CAPABILITY OF JITTER FILTERING 25nS 50nS 100nS 200nS 400nS 800nS 1.6uS
SMSC DS - TMC2005
Page 11
Rev. 10/24/2000
Option Feature for Jitter Filtering When any RX ports receive the bigger jitter than its allowance, the TMC2005 may fail to receive the data correctly and the network may be down.. However the below method to escape is effective for the case that a momentary big jitter occurs under a special condition like an optical transceiver. 1) Big jitter (BJ) mode The reference phase of the internal DPLL is changed from the first pulse to the second pulse by setting "0" to the big jitter mode pins (nBJX). This setup is effective for the case that a big jitter occurs when rising up from DC state as same as when using an optical transceiver with ATC function (refer to complement). Note: The delay time of the TMC2005 becomes 400nS (at 2.5Mbps) longer than the normal mode. The delay time limits the maximum cable length and maximum node number. [Complement] The big jitter may occur in the case of using an optical transceiver, especially an optical receiver that has an ATC circuit that controls threshold level in proportion to received light strength. The first pulse especially after long time idle has the big jitter but the second pulse is stabilized. 2) Changing polar of RX port In order to filter the jitter of edge in one side, it is effective to set reverse to pin SA, SB, SE to change the polarity of RX port. Note: Changing the polarity of RX port makes the delay time of the TMC2005 circuit a half bit (200nS) longer than original 2.5Mbps, and the delay time affects the maximum cable length and maximum node number.
SMSC DS - TMC2005
Page 12
Rev. 10/24/2000
APPLICATION NOTES
Example 1: A five ports HUB with HYC2485s in backplane mode.
HYC2485S Vref VCC nRXIN PH_B PH_A GND nTXEN nPULSE1
1 2 3 4 5 6 7 8
HYC2485S Vref VCC nRXIN PH_B PH_A GND nTXEN nPULSE1 1 2 3 4 5 6 7 8
HYC2485S Vref VCC nRXIN PH_B PH_A GND nTXEN nPULSE1
1 2 3 4 5 6 7 8
HYC2485S Vref VCC nRXIN PH_B PH_A GND nTXEN nPULSE1
1 2 3 4 5 6 7 8
FIGURE 1 - APPLICATION EXAMPLE 1
Only the TMC2005 and five transceivers are indicated in the above figure. Connect the other pins adequately. Example 2: A five ports HUB with HYC9088s and a optical transceiver(TODX270A) links the two physical layers; dipulse and fiber optics.
SMSC DS - TMC2005
Page 13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
HYC2485S Vref VCC nRXIN PH_B PH_A GND nTXEN nPULSE1
1 2 3 4 5 6 7 8
TXENB1 NC1 SE NC2 LE EXTRX ME VSS1 EXTTX VDD1 CKO VSS2 CKM2 CKM1 CKM0
46 RXINA0 47 SA 48 TXENA0 49 LA 50 RXINA1 51 MA 52 TXENA1 53 VDD6 54 VSS8 55 RXINB0 56 SB 57 TXENB0 58 LB 59 RXINB1 60 MB
VSS7 nPULSE1 nPULSE2 nP1BAK VDD5 nCKOEN nRST VSS6 nBJA nBJB nBJE nMBA nMBB nMBE nEXTOD
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
+5V
VSS5 VSS3 AVSS AGS LP RO TMC2005 AVDD VDD3 VDD4 VSS4 XTLO XTLI VDD2 nPLLTST RXFLT
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Rev. 10/24/2000
+5V
HYC9088S-SK
18 nPULSE2 19 DISABLE 20 nPULSE1
RX
HYC9088S-SK
7
nPULSE2 18 19 DISABLE 20 nPULSE1
RX
HYC9088S-SK
7
nPULSE2 18 DISABLE 19 nPULSE1 20
RX 7
HYC9088S-SK
18 nPULSE2 DISABLE 19 nPULSE1 20
9
GNDC1
OUT 1 GND1 2 3 TODX270AVCC1 4 GND2 5 GND3 6 LEDR 7 VCC2 8 IN
GNDC2
10
FIGURE 2 - APPLICATION EXAMPLE 2 Only the TMC2005 and five transceivers are indicated in the above figure. Connect the other pins adequately.
SMSC DS - TMC2005
Page 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TXENB1 NC1 SE NC2 LE EXTRX ME VSS1 EXTTX VDD1 CKO VSS2 CKM2 CKM1 CKM0
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
VSS7 nPULSE1 nPULSE2 nP1BAK VDD5 nCKOEN nRST VSS6 nBJA nBJB nBJE nMBA nMBB nMBE nEXTOD
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
RX 7
RXINA0 SA TXENA0 LA RXINA1 MA TXENA1 VDD6 VSS8 RXINB0 SB TXENB0 LB RXINB1 MB
TMC2005
VSS5 VSS3 AVSS AGS LP RO AVDD VDD3 VDD4 VSS4 XTLO XTLI VDD2 nPLLTST RXFLT
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Rev. 10/24/2000
Example 3: A five ports HUB with two optical transceivers, two HYC9088s, and a HYC2485S links three physical layers; fiber optics, dipulse, and AC-485.
GNDC2
10
9
GNDC1
OUT GND1 VCC1 TODX270A GND2 GND3 LEDR VCC2 IN
1 2 3 4 5 6 7 8
GNDC2
9
GNDC1
TODX270A VCC1 GND2 GND3 LEDR VCC2 IN
RX HYC9088S-SK nPULSE2 DISABLE nPULSE1
7 18 19 20
RX HYC9088S-SK nPULSE2 DISABLE nPULSE1
7 18 19 20
U? Vref VCC nRXIN PH_B PH_A GND nTXEN nPULSE1 1 2 3 4 5 6 7 8
HYC2485S
FIGURE 3 - APPLICATION EXAMPLE 3 Only the TMC2005 and five transceivers are indicated in the figure above. Connect the other pins properly.
SMSC DS - TMC2005
Page 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TXENB1 NC1 SE NC2 LE EXTRX ME VSS1 EXTTX VDD1 CKO VSS2 CKM2 CKM1 CKM0
OUT GND1
1 2 3 4 5 6 7 8
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
VSS7 nPULSE1 nPULSE2 nP1BAK VDD5 nCKOEN nRST VSS6 nBJA nBJB nBJE nMBA nMBB nMBE nEXTOD
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
+5v
RXINA0 SA TXENA0 LA RXINA1 MA TXENA1 VDD6 VSS8 RXINB0 SB TXENB0 LB RXINB1 MB
TMC2005
VSS5 VSS3 AVSS AGS LP RO AVDD VDD3 VDD4 VSS4 XTLO XTLI VDD2 nPLLTST RXFLT
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
10
Rev. 10/24/2000
Example 4: An on-board type HUB with a COM20020 and four optical transceivers in backplane mode.
+5V
GNDC2
10
9
GNDC1
TODX270A VCC1 GND2 GND3 LEDR VCC2 IN
GNDC2
GNDC2
10
9
GNDC1
OUT GND1 VCC1 TODX270A GND2 GND3 LEDR VCC2 IN
1 2 3 4 5 6 7 8
GNDC2
10
9
GNDC1
OUT GND1 VCC1 TODX270A GND2 GND3 LEDR VCC2 IN
1 2 3 4 5 6 7 8
TODX270A
9
GNDC1
OUT GND1 VCC1 GND2 GND3 LEDR VCC2 IN
1 2 3 4 5 6 7 8
nPULSE1 nTXEN COM20020
15 18
1 3 2
RXIN
17
FIGURE 4 - APPLICATION EXAMPLE 4 Only the TMC2005 and four transceivers with the COM20020 are indicated in the above figure. Connect the other pins adequately.
SMSC DS - TMC2005
Page 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TXENB1 NC1 SE NC2 LE EXTRX ME VSS1 EXTTX VDD1 CKO VSS2 CKM2 CKM1 CKM0
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
VSS7 nPULSE1 nPULSE2 nP1BAK VDD5 nCKOEN nRST VSS6 nBJA nBJB nBJE nMBA nMBB nMBE nEXTOD
OUT GND1
1 2 3 4 5 6 7 8
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
RXINA0 SA TXENA0 LA RXINA1 MA TXENA1 VDD6 VSS8 RXINB0 SB TXENB0 LB RXINB1 MB
TMC2005
VSS5 VSS3 AVSS AGS LP RO AVDD VDD3 VDD4 VSS4 XTLO XTLI VDD2 nPLLTST RXFLT
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
10
Rev. 10/24/2000
Example 5: An on-board type HUB with a COM20020 and four RS485 transceivers.
R nRE SN75176 DE D
1 2 3 4
R nRE SN75176 DE D
1 2 3 4
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
VSS7 nPULSE1 nPULSE2 nP1BAK VDD5 nCKOEN nRST VSS6 nBJA nBJB nBJE nMBA nMBB nMBE nEXTOD
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
+5V
RXINA0 SA TXENA0 LA RXINA1 MA TXENA1 VDD6 VSS8 RXINB0 SB TXENB0 LB RXINB1 MB
TMC2005
VSS5 VSS3 AVSS AGS LP RO AVDD VDD3 VDD4 VSS4 XTLO XTLI VDD2 nPLLTST RXFLT
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R nRE SN75176 DE D
1 2 3 4
R nRE SN75176 DE D
1 2 3 4
UA nPULSE1 nTXEN COM20020 15 18 1 3 2 1
RXIN
17
FIGURE 5 - APPLICATION EXAMPLE 5 Only the TMC2005 and four transceivers with the COM20020 are indicated in the above figure. Connect the other pins adequately.
SMSC DS - TMC2005
Page 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TXENB1 NC1 SE NC2 LE EXTRX ME VSS1 EXTTX VDD1 CKO VSS2 CKM2 CKM1 CKM0
Rev. 10/24/2000
Example 6: An on-board type HUB with a COM20020, two HYC2485Ss, and two HYC9088s links two different physical layers; dipulse and AC-485.
U? Vref VCC nRXIN PH_B PH_A GND nTXEN nPULSE1 1 2 3 4 5 6 7 8
HYC2485S
HYC2485S
RX HYC9088S-SK nPULSE2 DISABLE nPULSE1
7 18 19 20
RX HYC9088S-SK nPULSE2 DISABLE nPULSE1
7 18 19 20
nPULSE1 nTXEN COM20020
15 18
RXIN
17
2
1
FIGURE 6 - APPLICATION EXAMPLE 6 Only the TMC2005 and four transceivers with the COM20020 are indicated in the above figure. Connect the other pins adequately.
SMSC DS - TMC2005
Page 18
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Vref VCC nRXIN PH_B PH_A GND nTXEN nPULSE1
1 2 3 4 5 6 7 8
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
VSS7 nPULSE1 nPULSE2 nP1BAK VDD5 nCKOEN nRST VSS6 nBJA nBJB nBJE nMBA nMBB nMBE nEXTOD
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
+5V
TXENB1 NC1 SE NC2 LE EXTRX ME VSS1 EXTTX VDD1 CKO VSS2 CKM2 CKM1 CKM0
RXINA0 SA TXENA0 LA RXINA1 MA TXENA1 VDD6 VSS8 RXINB0 SB TXENB0 LB RXINB1 MB
TMC2005
VSS5 VSS3 AVSS AGS LP RO AVDD VDD3 VDD4 VSS4 XTLO XTLI VDD2 nPLLTST RXFLT
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Rev. 10/24/2000
Example 7: An eight port HUB with two TMC2005s, two HYC2485Ss, two HYC9088s, two SN75176s, and two optical transceivers links four different physical layers; AC-485, dipulse, RS485, and fiber optics.
Vref 2 HYC2485S VCC nRXIN PH_B PH_A GND nTXEN nPULSE1 3 4 5 6 7 8 1 3 4 5 6 7 8 7 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS7 nPULSE1 nPULSE2 nP1BAK VDD5 nCKOEN nRST VSS6 nBJA nBJB nBJE nMBA nMBB nMBE nEXTOD 1 +5V
Vref 2 HYC2485S VCC nRXIN PH_B PH_A GND nTXEN nPULSE1 RX
HYC9088S-SK
18 nPULSE2 19 DISABLE 20 nPULSE1 RX 7
HYC9088S-SK
18 nPULSE2 19 DISABLE 20 nPULSE1 R 1 2 3 4 1 2 3 4 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
SN75176a nRE DE D R SN75176a nRE DE D
VSS7 nPULSE1 nPULSE2 nP1BAK VDD5 nCKOEN nRST VSS6 nBJA nBJB nBJE nMBA nMBB nMBE nEXTOD
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TXENB1 NC1 SE NC2 LE EXTRX ME VSS1 EXTTX VDD1 CKO VSS2 CKM2 CKM1 CKM0
RXINA0 SA TXENA0 LA RXINA1 MA TXENA1 VDD6 VSS8 RXINB0 SB TXENB0 LB RXINB1 MB
TMC2005
VSS5 VSS3 AVSS AGS LP RO AVDD VDD3 VDD4 VSS4 XTLO XTLI VDD2 nPLLTST RXFLT
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUT GND1 VCC1 GND2 TODX270A GND3 LEDR VCC2 IN GNDC2 GNDC1 9
1 2 3 4 5 6 7 8
10
OUT GND1 VCC1 GND2 TODX270A GND3 LEDR VCC2 IN 9 GNDC1 GNDC2
1 2 3 4 5 6 7 8
FIGURE 7 - APPLICATION EXAMPLE 7 Only the TMC2005 and eight transceivers are indicated in the above figure. Connect the other pins adequately.
SMSC DS - TMC2005
Page 19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
TXENB1 NC1 SE NC2 LE EXTRX ME VSS1 EXTTX VDD1 CKO VSS2 CKM2 CKM1 CKM0
RXINA0 SA TXENA0 LA RXINA1 MA TXENA1 VDD6 VSS8 RXINB0 SB TXENB0 LB RXINB1 MB
10
TMC2005
VSS5 VSS3 AVSS AGS LP RO AVDD VDD3 VDD4 VSS4 XTLO XTLI VDD2 nPLLTST RXFLT
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Rev. 10/24/2000
Example 8: A sixteen port HUB with four TMC2005s, eight optical transceivers, and eight HYC2485Ss links two different physical layers; fiber optics and AC-485.
10 G N OUT DC ND1 G 2 VCC1 G TODX270AaN D 2 G GN ND3 D CL E D R VCC2 1 IN 9 1 2 3 4 5 6 7 8
+5V 454 44 34 24 1403 93 83 73 6353 43 33 231 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VS P n P D C V S B B B nM n E n nP V n nR n n n nM nM 1 D KO S J J JE BB X S7ULUL B 5 ST 6 A B BA B E T VSS5 RXINA0 OD SE A K EN SE SA VSS3 TXENA0 1 2 AVSS LA AGS RXINA1 LP MA RO TXENA1 AVDD TMC2005 VDD6 VDD3 VSS8 VDD4 RXINB0 VSS4 SB XTLO TXENB0 XTLI TX LB VDD2 EX EX RXINB1 EN V S V D K CK K P L L T S T VS C C K n TR TT C MB B1NC N C E ME 1 D 1 S2M2 M0 X F L T M1 R SE L X S X 12 O 1 2 3 4 5 6 7 8 9 1 0111 21 31 415 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
+5V
R1 250
10 G N OUT DC ND1 G 2 VCC1 G TODX270AaN D 2 G GN ND3 D CL E D R VCC2 1 IN 9 1 2 3 4 5 6 7 8
4 54 44 34 2414 03 93 83 7363 53 43 3323 1 10 G N OUT DC ND1 G 2 VCC1 G TODX270AaN D 2 G GN ND3 D CL E D R VCC2 1 IN 9 1 2 3 4 5 6 7 8 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VS n P P nC R S B B B nM n E nP n VD n V n n n nM nM S7UL L B KO T 6 A JEBA B E U 1 D S S J JB B B XT 30 RXINA0 SE E K 5 SA O D VSS5 2 9 EN SA VSS3 2 8 TXENA0 1 2 A V S S 27 LA AGS 2 6 RXINA1 L P 25 MA RO TXENA1 AVDD 24 TMC2005 23 VDD6 VDD3 22 VSS8 VDD4 21 RXINB0 VSS4 2 0 SB XTLO 19 TXENB0 XTLI 18 TX LB VDD2 17 EX EX EN C C CK RXINB1 V S VD VS K K P L L T S T 1 6 n N T R S TT CK M 2 M0 MB B1NC E C E M E 1 D 1 S2 M1 RXFLT X O 1S 2 L X 1 2 3 4 56 7 8 9 101 11 21 3141 5
10 G N OUT DC ND1 G 2 VCC1 G TODX270AaN D 2 G GN ND3 D CL E D R VCC2 1 IN 9 1 2 3 4 5 6 7 8
4 54 44 34 2414 03 93 83 7363 53 43 3323 1 1 2 3 4 5 6 7 8 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VS n P P nC R S B B B nM n E nP n VD n V n n n nM nM U 1 D KO S J JB S7UL L B 5 S T 6 A JEBA B E VSS5 3 0 B B XT RXINA0 OD 29 SE E K EN SA SA VSS3 2 8 TXENA0 1 2 A V S S 27 LA AGS 2 6 RXINA1 L P 25 MA RO 24 TXENA1 AVDD 23 TMC2005 VDD6 VDD3 22 VSS8 VDD4 21 RXINB0 VSS4 2 0 SB XTLO 19 TXENB0 XTLI 18 TX LB VDD2 EX EX RXINB1 EN V S VD VS K K P L L T S T 1 7 n TT CK C C C K 16 N TR MB B1NC E C E M E 1 D 1 S2 M1 RXFLT M 2 M0 S SX O 1 2LX 1 2 3 4 5 6 7 8 9 101 11 21 3141 5
HYC2485Sa Vref VCC nRXIN PH_B PH_A GND nTXEN nPULSE1
HYC2485Sa Vref VCC nRXIN PH_B PH_A GND nTXEN nPULSE1
1 2 3 4 5 6 7 8
HYC2485Sa Vref VCC nRXIN PH_B PH_A GND nTXEN nPULSE1
1 2 3 4 5 6 7 8
4 54 44 34 2414 03 93 83 7363 53 43 3323 1 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 nP n VD n V n n n nM nM VS n P P nC R S B B B nM n E S7 U 1 B KO S J JB B B XT RXINA0 UL L D 5 S T 6 A JEBA B E D VSS5 3 0 O 29 SE E K EN SA SA VSS3 2 8 TXENA0 1 2 A V S S 27 LA AGS 2 6 RXINA1 L P 25 MA RO 24 TXENA1 AVDD 23 TMC2005 VDD6 VDD3 VSS8 VDD4 22 21 RXINB0 VSS4 2 0 SB XTLO 19 TXENB0 XTLI 18 TX LB VDD2 17 EX EX RXINB1 EN V S VD VS K K P L L T S T 1 6 n TT CK C C C K N TR MB B1NC E C E M E 1 D 1 S2 M1 RXFLT M 2 M0 S SX O 1 2LX 1 2 3 4 5 6 7 8 9 101 11 21 3141 5
HYC2485Sa Vref VCC nRXIN PH_B PH_A GND nTXEN nPULSE1
1 2 3 4 5 6 7 8
FIGURE 8 - APPLICATION EXAMPLE 8 Only the TMC2005s, and eight transceivers are indicated in the above figure. Connect the other pins adequately. Note: When connecting several TMC2005s on the same board with the open-drain outputs like Fig. 8, four TMC2005s are maximum to connect and 5Mbps is the maximum data rate.
SMSC DS - TMC2005
Page 20
Rev. 10/24/2000
PORT GROUP
The five ports can be divided into three groups (group A: two ports, group B: two ports, extension port: one port) and each group can select TX/RX polar, noise cut mode, and big jitter mode respectively. Select pins for each group are as follows: FUNCTION RECEIVE TRANSMIT RX POLARITY TX POLARITY TX CONTROL NOISE CUT BIG JITTER EXTENSION Various Setup Example For Operation Mode Setup To Each Port LA, LB, LE MA, MB, ME RX POLAR TX POLAR TRANSCEIVER 0 1 Active Low Active Low HYC2485S/HYC2488S 1 0 Active High Active High Optical Transceiver 0 1 Active High Active Low HYC9088/HYC9068 1 1 Active Low Active High RS485 Transceiver GROUP A RXINA0, 1 TXENA0, 1 SA LA MA nMBA nBJA GROUP B RXINB0, 1 TXENB0, 1 SB LB MB nMBB nBJB EXTENSION EXTRX EXTTX SE LE ME nMBE nBJE nEXTOD
SA, SB, SE 1 0 0 1
Note for Unused port Unused ports can be left open because RX port (RX input), RX polar (S input), TX polar (L input), TX control (M input) pins have internal pull-up resistors. Because of internal pull-up resistors, select pins for noise cut (nMB input), big jitter (nBJ input) can be left open when used for setting "OFF".
Example for Power-On Reset Circuit
+5V
Rp TMC2005
10K 3 Cp 4.7uF 2 39 nRST 1 2 MB3771/NJM2103 1 2T 2T 2T 2T 2T 2T 2T 8 7 +5V 6 5 39
TMC2005
nRST
Ct
0.1uF
3 4
POWER-ON RESET CIRCUIT (C, R)
POWER-ON RESET CIRCUIT (POR IC)
FIGURE 9 - POWER-ON RESET
SMSC DS - TMC2005
Page 21
Rev. 10/24/2000
CONNECTING THE TMC2005 WITH INTERNAL PLL
When using the TMC2005 at data rate 2.5Mbps or lower, it is not necessary to use internal PLL. Leave the loop filter pins (RO, LP) open and connect AGS to the Ground. The pins for the analog power supply (AVSS, AVDD) may connect to digital power supply. When using the TMC2005 at data rate 5Mbps or higher, the internal PLL has to be used as a clock multiplier. PCB layout must follow the guidelines at Figure 10, refer to Notes 1 through 5.
PWR Plane Gnd Plane
TMC2005
VSS5 VSS3
30 0.1uF (c) 29 10uF (b) 0.1uF (a)
AVSS AGS LP RO VAA VDD3 VDD4
28 27 2400pF 26 68K 25 24 23 22
FIGURE 10 - PLL PATTERN LAYOUT Note 1: Prohibit the patterns for LP and RO from occupying the area of digital power supply. Use the area of analog power supply between VAA and AVSS. Note 2: Encircle the pattern between LP, RO and AGS with wide pattern of analog ground. Note 3: Connect the analog power supply "VAA" with 0.1 uF condenser (a) with in 1/8 inch (~ 3.2mm) from VAA pin. Note 4: In order to filter the jitter of low frequency, connect a 10 uF condenser (b) in parallel with the condenser (a). Note 5: Place 0.1 uF bypass condenser (c) within 1/4 inch (~ 6.4mm) from VDD3 and VSS3. Connect the ground side of a condenser (c) at the place (*) where AVSS returns to GND plane.
SMSC DS - TMC2005
Page 22
Rev. 10/24/2000
Method To Connect A Crystal Clock Connect with external parts as follows:
TMC2005
Cin XTLI 19 22pF Rfb
5.1K ohm
XTAL
20MHz
XTLO
20
Rout 51ohm
Cout
22pF
FIGURE 11 - CONNECTING THE CRYSTAL CLOCK
Note 1: When designing a printed circuit board, keep the patterns as short as possible and don't cross with other patterns. Note 2: When using an external clock like an oscillator module, connect it to XTLI pin and leave XTLO pin open. When designing a printed circuit board, wire between XTLI pin and oscillator should be short as possible.
nPLLTST pin nPLLTST must be connect toVDD. The rest of input pins have pull-up resistors built in, but nPLLTST pin does not have the pull-up resistor. Clock signal cannot ditributed into the TMC2005 if nPLLTST pin is connected GND or is left open.
SMSC DS - TMC2005
Page 23
Rev. 10/24/2000
CASCADING CONNECTION
HUBs can be connected in cascade by using the ports as Fig. 12. In the case of cascade connection, it is necessary to consider how many HUBs can exist in serial. The maximum delay between input port and output port is 650ns @2.5Mbps at the TMC2005. It is equivalent to the propagation delay when a cable length is 135m. For example, if every cable length is 10m in Figure 12, the longest distance is physically 50m but it is electrically 590m because of multiplying 10m by 5 and 135m by 4, and the total propagation delay becomes 2.8uS. For analyzing the network timing, consider the delay caused by HUBs. In the ARCNET protocol, it is defined that the longest distance between nodes is the maximum 6.4Km. For example, if 20 TMC2005s exist between nodes in the longest distance, the actual cable length is 3.7Km because of deducting 135m by 20 in converting to cable length from 6.4Km.
TMC2005
TMC2005
TMC2005
TMC2005
1 2 3 4 5
1 2 3 4 5
1 2 3 4 5
Port Port Port Port Port
Port Port Port Port Port
Port Port Port Port Port
1 2 3 4 5
1 2 3 4 5
1 2 3 4 5
NODE
FIGURE 12 - CASCADE CONNECTION OF 4 HUBS
Two examples of eight ports HUBs using two TMC2005s are shown in Fig. 13 and 14. If connecting as in Fig. 13, eight TMC2005s exist between the nodes at both far ends. On the other hand, when assigning two ports for cascading connection to the same TMC2005, the number of TMC2005 in serial connection can be down to the number of HUBs plus two, which can reduce the propagation delay.
SMSC DS - TMC2005
Page 24
1 2 3 4 5 NODE
Port Port Port Port Port
1 2 3 4 5
Rev. 10/24/2000
HUB 1
TMC2005 TMC2005
HUB2
TMC2005 TMC2005 TMC2005
HUB 3
TMC2005 TMC2005
HUB4
TMC2005
1 2 3 4
2 3 4 5
1 2 3 4
2 3 4 5
1 2 3 4
2 3 4 5
1 2 3 4
1 2 3 4
2 3 4 5
1 2 3 4
2 3 4 5
1 2 3 4
2 3 4 5
1 2 3 4
NODE
FIGURE 13 - CASCADE CONNECTION OF 8 PORT HUB
HUB 1
TMC2005 TMC2005
HUB2
TMC2005 TMC2005
HUB 3
TMC2005 TMC2005
HUB4
TMC2005 TMC2005
1 2 3 4
2 3 4 5
1 2 3 4
2 3 4 5
1 2 3 4
2 3 4 5
1 2 3 4
1 2 3 4
2 3 4 5
1 2 3 4
2 3 4 5
1 2 3 4
2 3 4 5
1 2 3 4
NODE
FIGURE 14 - CASCADE CONNECTION OF 8 PORT HUB
SMSC DS - TMC2005
Page 25
2 3 4 5
2 3 4 5
2 3 4 5
2 3 4 5
NODE
NODE
Rev. 10/24/2000
Fig.15 shows a 16 ports HUB with four TMC2005s connected by open-drain ports. When assigning two ports for cascade connection to the same TMC2005, the number of TMC2005s for serial connection can be reduced to the number of HUBs plus two.
HUB2
HUB 3
TMC2005
1 2 3 4
TMC2005
1 2 3 4
TMC2005
1 2 3 4
TMC2005
1 2 3 4
TMC2005
1 2 3 4
TMC2005
1 2 3 4
TMC2005
1 2 3 4
TMC2005
1 2 3 4 1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
HUB 1
TMC2005
1 2 3 4
1 2 3 4
HUB 4
TMC2005
1 2 3 4
TMC2005
1 2 3 4
TMC2005
1 2 3 4
TMC2005
1 2 3 4
TMC2005
1 2 3 4
TMC2005
1 2 3 4
TMC2005
1 2 3 4 1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
NODE
1 2 3 4
NODE
FIGURE 15 - CASCADE CONNECTION OF 16 PORT HUB Note: When connecting TMC2005 by open-drain output on a board, connecting TMC2005s must be four or less, and the data rate must be 5Mbps or slower. The pattern of open-drain output has to be as short as possible (less than 15cm).
SMSC DS - TMC2005
Page 26
Rev. 10/24/2000
Ring Network With the TMC2005 The reliability of the network can be improved by connecting every node in a ring, because the communication is maintained through the reverse route even if the cable is cut at a point. However ARCNET controller alone can not support ring, because ARCNET is a half-duplex communication system. Using HUBs makes possible for ARCNET to built a ring network as in Fig.16. This configuration is available only for using fiber optics.
Optical Transceiver COM20020
TMC2005 A B
Optical Fiber
COM20020
TMC2005
TMC2005
COM20020
nRST TXEN nRESET
CK TMC2005 TXEN of any port
CT
COM20020
FIGURE 16 - RING CONFIGURATION Note 1: Noise may cause an endless loop in a ring system, and the network may hang up. Therefore take care of designing the patterns between TMC2005 and transceiver or cabling of system. Example for system hang-up A noise occurs only at "A" point in Figure 16. The noise propagates clockwise on the network. TMC2005 detects the noise that came back through the ring. The noise causes an endless loop in the ring. Example for no hang-up Any noise occurs at "A" and "B" points in Figure 16 at the same time. The noise propagates to both directions in the network. An endless loop doesn't occur because TMC2005s in the middle absorb the noise from both sides. Note 2: Place a watch dog timer on one of the TMC2005 in at least one ring. To protect from hang-up the detecting time of the watch dog timer should be set to longer than 2.7 mS (@ 2.5Mbps) that is the burst time in the ARCNET protocol. Note 3: Consider that a total of each segment delay time (cable delay, TMC2005 delay, driver delay and receiver delay) between HUBs in a network is less than 5.6uS (@ 2.5Mbps). The maxmimum distance between HUBs is approximiately 1000m (@ 2.5Mbps).
SMSC DS - TMC2005
Page 27
Rev. 10/24/2000
ARCNET (@2.5Mbps)
400nS
400nS
S=1 RX Input Normal Mode S=0 RX Input Backplane Mode
L=0, M=x TX Output (Rx Port) L=0, M=1 TX Output (Other Ports)
75 - 125nS
5.6uS
275 - 575nS
200nS
L=1, M=0 TX Output (Other Ports)
275 - 575nS
100nS
nPULSE1
375 - 675nS 100nS
nPULSE2
275 - 575nS
200nS
nP1BAK
FIGURE 17 - TIMING CHART
SMSC DS - TMC2005
Page 28
Rev. 10/24/2000
OPERATIONAL DESCRIPTION
MAXIMUM GUARANTEED RATINGS* Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. (Note) When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes or "glitches" on their output when the AC power is switch on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists it is suggested that a clamp circuit be used. Vss = 0V ITEM POWER SUPPLY VOLTAGE INPUT VOLTAGE OUTPUT VOLTAGE AMBIENT TEMPERATURE STANDARD OPERATING CONDITION Vss = 0V ITEM POWER SUPPLY VOLTAGE AMBIENT TEMPERATURE SYMBOL VDD VIN VOUT Tstg RATING -0.3 +7.0 -0.3 VDD +0.3 -0.3 VDD +0.3 -40 +125 UNIT V V V C
SYMBOL VDD Ta
RATING 4.5 - 5.5 0 - +85
UNIT V C
DC CHARACTERISTIC - INPUT PIN SYMBOL ITEM VIH High Level Input Voltage VIL Low Level Input Voltage IIH High Level Input Current IIL Low Level Input Current IIL With pull-up IOZ Output Leak Current IDD Dissipation Current
CONDITION
MIN 2.2 -10 -10 -200 -10
MAX 0.8 10 10 -10 10 100
VIN=VDD VIN=VSS Vin=VSS VOUT=VDD or VSS Operating
UNIT V V uA uA uA uA mA
SMSC DS - TMC2005
Page 29
Rev. 10/24/2000
DC CHARACTERISTIC - OUTPUT PIN SYMBOL ITEM VOH High Level Output Voltage VOH VOL VOL High Level Output Voltage Low Level Output Voltage Low Level Output Voltage
CONDITION IOH=-4mA IOH=-8mA IOL=4mA IOL=8mA
MIN 2.4 2.4
MAX
UNIT V V V V
0.4 0.4
PIN 1,9,43,48, 52,57 11,42,44 1,9,43,48, 52,57 11,42,44
AC CHARACTERISTIC - CLOCK and RESET ITEM SYMBOL Generating Static Time tx Clock Cycle tCYC Clock Frequency Deflection tCDF Clock Pulse Width tCW Reset Pulse Width ttRSW Note 1: Use only F=20MHz Note 2: VDD=4.5V
MIN
TYP 50
MAX 4 100
-100 20 200
UNIT mS nS ppm nS nS
CONDITION Note 1 Note 1 Note 1 Note 1
XTLI
tCW tCW tCYC
nRST
tRSW
FIGURE 18 - CLOCK AND RESET
SMSC DS - TMC2005
Page 30
Rev. 10/24/2000
TMC2005 60 PIN QFP PACKAGE OUTLINE
D D1
Ze
46
45
31 30
E1 E
60
60 1
16 15
1
Zd
SYMBOL D D1 E E1 Ze Zd
MIN (mm) 18.6 13.8 18.6 13.8
TYP (mm) 18.9 14.0 18.9 13.0 1.40 typ 1.40 typ
MAX (mm) 19.2 14.2 19.2 14.2
SMSC DS - TMC2005
Page 31
Rev. 10/24/2000
A2
A
b
bbb M
e
aaa
A1
SYMBOL A A1 A2 B E aaa bbb
MIN (mm) 0.13 2.50 0.25
TYP (mm) 0.23 2.70 0.35 0.80 BSC 0.15 0.16
MAX (mm) 3.05 0.33 2.90 0.45
c L
SYMBOL c L
MIN (mm) 0.10 1.15
TYP (mm) 0.15 1.35
MAX (mm) 0.25 1.55
SMSC DS - TMC2005
Page 32
Rev. 10/24/2000

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